NVIC
The Nested Vectored Interrupt Controller manages Cortex-M interrupt enable, pending state and priority. Implementations provide a device-specific number of priority bits.
ARCHITECTURE
Identify the block, clock/source dependencies, data path and interfaces.
CONFIGURE
Follow the target reference manual and change only documented fields.
VERIFY
Define the expected register state, timing or signal before running the test.
DEBUG
Inspect software state and measure hardware behavior rather than guessing.
From manual to measurement
- Read the architecture/reference-manual section.
- Identify clocks, pins, memory, interrupts and dependencies.
- Calculate required timing or configuration values.
- Implement the smallest working configuration.
- Build with warnings enabled and flash the target.
- Inspect registers and measure the external behavior.
- Document failures, assumptions and the final fix.
KEY TAKEAWAY
The Nested Vectored Interrupt Controller manages Cortex-M interrupt enable, pending state and priority. Implementations provide a device-specific number of priority bits.